View AN666_5424853.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 0.1 9/12 copyright ? 2012 by silicon laboratories AN666 AN666 u sage g uide for s i m3u1 xx , s i m3c1 xx , and s i m3l1 xx dma and dtm m odules 1. introduction the direct memory access (dma) (sim3u1xx, sim3c1xx , and sim3l1xx) and data transfer manager (dtm) (sim3l1xx) modules are complex data management modules intended to autonomously transfer data between peripherals and memory. these modules can save system power consumption by allowing the core to enter a low power state or process data in parallel to improve perfor mance. this document discusses usage models for these modules. figure 1. transferring data using the dma and dtm modules 2. key points this key topics of this document are: ?? using the dma in a basic memory-to-memory data transfer ?? using the dma from a peripheral-to-memory data transfer ?? using the dma from memory to a peripheral data transfer ?? complex multi-channel dma transfers using the data transfer manager (sim3l1xx devices only) 3. relevant documentation precision32 application notes are listed on the following website: www.s ilabs.com/32bit-appnotes. ?? an725: advanced low power techniques for sim3l1xx devices ?? an667: getting start ed with the silicon la bs precision32 ide ?? an670: integrat ing silicon labs sim3xxxx devi ces into the keil vision ide sim3xxxx address space (ram) dma channel 1 dma channel 0 usart0 rx usart0 tx
AN666 2 rev. 0.1 4. dma overview the dma consists of two modules: dma controller (d mactrl) and dma peripheral crossbar (dmaxbar). the controller provides a single access point for all 16 (sim3u1xx and sim3c1xx) or 10 (sim3l1xx) dma channels and the global dma controls. the controlle r is also responsible for handling ar bitration between channels. the dma peripheral crossbar assigns channels to a peripheral. wh en assigned and properly configured, the peripheral?s data request signal will trigger a dm a channel to transfer data. figure 2 shows a block diagram of the dma controller and dma peripheral crossbar. figure 2. dmactrl and dmach block diagram the channels have controls and flags in the dmactrl re gisters. in addition, each channel has one or more transfer descriptors stored in memory that describe t he data transfer in detail. each channel can have primary, alternate, or scatter-gather desc riptors. the baseptr and aba septr registers in the co ntroller point to the starting address of th ese descriptors in memory. fi rmware sets the baseptr field, and the cont roller hardware automatically sets the abaseptr fiel d based on the number of channe ls implemented in the module. each channel has separate enables, alternate enables, masks, software requests, programmable priority, and status flags. the channels operate indepe ndently, but have a fixed arbitration order. the state field reports the current status of the dma co ntroller, and the dmaens bit indicates whether the global dma enable is set. dmaxbarn module dmactrln module channel control channel status global controller state and enable channel software transfer request arbitration sim3xxxx ram dma channel n (dman_chx) source pointer destination pointer configuration dma channel 0 (dman_ch0) source pointer destination pointer configuration dma channel 1 (dman_ch1) source pointer destination pointer configuration peripheral 0.0 peripheral 0.1 peripheral 0.2 peripheral 0.3 peripheral 0.x peripheral 1.0 peripheral 1.1 peripheral 1.2 peripheral 1.3 peripheral 1.y peripheral n.0 peripheral n.1 peripheral n.2 peripheral n.3 peripheral n.z
AN666 rev. 0.1 3 4.1. dma channel transfer descriptors each channel has transfer descriptors stored in memory that describe the data transfer in detail. each descriptor is composed of four 32-bit words in memory organized as follows: 1. source end pointer (word 1) : the address of the last source data in the transfer. 2. destination end pointer (word 2) : the last destination address of the transfer. 3. channel configuration (word 3) : configuration details for the transfer. 4. alignment padding (word 4) : not used by the dma controller. firmware may use this word for any purpose. each channel can have primary, alternate, and scatter- gather descriptors. the primary and alternate descriptors are organized in contiguous blocks in memory for each of the channels. the spacing fo r these descriptors is fixed, so any unused channels must still be ac counted for when placing descriptor s in memory. the primary descriptors must be placed at the start of an address block sized for both the primary and alternate descriptors. for sim3u1xx, sim3c1xx, and sim3l1xx devices that implement 16 or 10 dma ch annels, the baseptr points to the start of the primary descriptors and is 23 bits wide. the valid addres ses for the baseptr field are multiples of 256 (0x0000_0100), and the required memory for all primary and alternate descriptors for 16 channels is 512 bytes. the scatter-gather descriptors are more flexible and can appear anywhere in memory. channel 0?s primary descriptor begins at address offset 0x0000, channel 1?s primary descriptor starts at offset 0x0010, and so on. the alternate descriptors begin at th e next memory block (256 bytes), regardless of whether or not the primary descriptors for the channels are in use. firmware originally sets the channe l configuration descriptor ; the dma controller will modi fy this word as the transfer progresses, so firmware should not write to this descriptor until any active transfers for the channel are complete. figure 3 shows the fixed memory co nfiguration for the descriptors.
AN666 4 rev. 0.1 figure 3. channel transfer descriptor memory configuration abaseptr sim3xxxx address space (ram) srcend dstend config channel x srcend dstend config baseptr channel 0 srcend dstend config channel 1 primary structures srcend dstend config channel 0 srcend dstend config channel 1 srcend dstend config channel x alternate structures srcend dstend config channel 0 sg 1 srcend dstend config channel 0 sg 2 (optional) scatter-gather structures
AN666 rev. 0.1 5 4.1.1. channel transfer descriptors table 1, table 2, and table 3 describe the source end pointer, destination pointer, and configuration descriptors for the primary, alternate, and scatter-gather dma channel descriptors. address in channel transfer descriptor: 0x0000 address in channel transfer descriptor: 0x0004 table 1. dma0_chx_srcend: source end pointer bit31302928272625242322212019181716 name srcend[31:16] bit1514131211109876543210 name srcend[15:0] bit name function 31:0 srcend source end pointer. this field is the address of the last source data in the dma transfer. table 2. dma0_chx_dstend: destination end pointer bit31302928272625242322212019181716 name dstend[31:16] bit1514131211109876543210 name dstend[15:0] bit name function 31:0 dstend destination end pointer. this field is the last destinat ion address of the dma transfer.
AN666 6 rev. 0.1 address in channel transfer descriptor: 0x0008 table 3. dma0_chx_config: channel configuration bit31302928272625242322212019181716 name dstaimd dstsize srcaimd srcsize reserved rpower[3:2] bit1514131211109876543210 name rpower[1:0] ncount reserved tmd bit name function 31:30 dstaimd destination address increment mode. this field must be set to a value that's equal to or greater than the dstsize setting. 00: the destination address increments by one byte after each data transfer. 01: the destination address increments by one half-word after each data transfer. 10: the destination address increments by one word after each data transfer. 11: the destination address does not increment. 29:28 dstsize destination data size select. the destination size (dstsize) must equal the source size (srcsize). 00: each dma destination data transfer writes a byte. 01: each dma destination data transfer writes a half-word. 10: each dma destination data transfer writes a word. 11: reserved. 27:26 srcaimd source address increment mode. this field must be set to a value that's equal to or greater than the srcsize setting. 00: the source address increments by one byte after each data transfer. 01: the source address increments by one half-word after each data transfer. 10: the source address increments by one word after each data transfer. 11: the source address does not increment. 25:24 srcsize source data size select. the destination size (dstsize) must equal the source size (srcsize). 00: each dma source data transfer reads a byte. 01: each dma source data transfer reads a half-word. 10: each dma source data transfer reads a word. 11: reserved. 23:18 reserved must write 0 to this field.
AN666 rev. 0.1 7 17:14 rpower transfer size select. this field determines the number of data transfers between each dma channel re-arbi- tration. the number of data transfers is given by: this field is ignored for peripherals that su pport single data requests only. a value of 0 for rpower should be used for channels interfacing with these types of peripherals. 13:4 ncount transfer total. this field is the total number of transfers for the dma channel. the total number is ncount + 1, so software re quiring a total of 4 transfer s would set the ncount field to 3. the dma controller decrements this field as transfers are made. 3 reserved must write 0 to this bit. 2:0 tmd transfer mode. 000: stop the dma channel. 001: use the basic transfer ty pe (single descriptor only). 010: use the auto-request transfer type (single descriptor only). 011: use the ping-pong transfer type (primary and alternate descriptors). 100: use the memory scatter-gather primar y transfer type (primary, alternate, and scattered descriptors). 101: use the memory scatter-gather alternat e transfer type (primary, alternate, and scattered descriptors). 110: use the peripheral scatter-gather prim ary transfer type (primary, alternate, and scattered descriptors). 111: use the peripheral scatter-gather alte rnate transfer type (primary, alternate, and scattered descriptors). bit name function number of transfers 2 rpower =
AN666 8 rev. 0.1 4.2. dma peripheral crossbar peripherals are assigned to various channels, and th e dma crossbar can be used to assign a channel to a particular peripheral. these assignments are shown in table 4. table 4. dma crossbar channel peripheral assignments for sim3u1xx devices peripheral dma channel 0 dma channel 1 dma channel 2 dma channel 3 dma channel 4 dma channel 5 dma channel 6 dma channel 7 dma channel 8 dma channel 9 dma channel 10 dma channel 11 dma channel 12 dma channel 13 dma channel 14 dma channel 15 aes0 rx ? ? aes0 tx ? ? aes0 xor ? ? dmaxt0 ???????????????? dmaxt1 ???????????????? epca0 capture ?? ?? epca0 control ?? ?? i2c0 rx ? ? ? i2c0 tx ? ? i 2 s rx ?? ?? i 2 s tx ?? ?? idac0 ? ? ?? idac1 ?? ?? saradc0 ? ?? saradc1 ? ? ? spi0 rx ? ? spi0 tx ? ? spi1 rx ? ? spi1 tx ? ? ? timer0l overflow ?? ? ? ? timer0h overflow ? ? ? ? ? ? ? timer1l overflow ?? ? ? ? timer1h overflow ?? ? ? ? ? ?
AN666 rev. 0.1 9 usart0 rx ? ? ? ? ? usart0 tx ? ? ? ? usart1 rx ? ? ? usart1 tx ? ? ? usb0 ep1 in ? ? usb0 ep2 in ? ? usb0 ep3 in ? ? usb0 ep4 in ? ? usb0 ep1 out ? ? usb0 ep2 out ? ? usb0 ep3 out ? ? usb0 ep4 out ? ? software trigger ???????????????? table 5. dma crossbar channel peripheral assignments for sim3c1xx devices peripheral dma channel 0 dma channel 1 dma channel 2 dma channel 3 dma channel 4 dma channel 5 dma channel 6 dma channel 7 dma channel 8 dma channel 9 dma channel 10 dma channel 11 dma channel 12 dma channel 13 dma channel 14 dma channel 15 aes0 rx ? ? aes0 tx ? ? aes0 xor ? ? dmaxt0 ???????????????? dmaxt1 ???????????????? epca0 capture ?? ?? epca0 control ?? ?? table 4. dma crossbar channel peripheral assignments for sim3u1xx devices peripheral dma channel 0 dma channel 1 dma channel 2 dma channel 3 dma channel 4 dma channel 5 dma channel 6 dma channel 7 dma channel 8 dma channel 9 dma channel 10 dma channel 11 dma channel 12 dma channel 13 dma channel 14 dma channel 15
AN666 10 rev. 0.1 i2c0 rx ? ? ? i2c0 tx ? ? i 2 s rx ?? ?? i 2 s tx ?? ?? idac0 ? ? ?? idac1 ?? ?? saradc0 ? ?? saradc1 ? ? ? spi0 rx ? ? spi0 tx ? ? spi1 rx ? ? spi1 tx ? ? ? timer0l overflow ?? ? ? ? timer0h overflow ? ? ? ? ? ? ? timer1l overflow ?? ? ? ? timer1h overflow ?? ? ? ? ? ? usart0 rx ? ? ? ? ? usart0 tx ? ? ? ? usart1 rx ? ? ? usart1 tx ? ? ? software trigger ???????????????? table 5. dma crossbar channel peripheral assignments for sim3c1xx devices (continued) peripheral dma channel 0 dma channel 1 dma channel 2 dma channel 3 dma channel 4 dma channel 5 dma channel 6 dma channel 7 dma channel 8 dma channel 9 dma channel 10 dma channel 11 dma channel 12 dma channel 13 dma channel 14 dma channel 15
AN666 rev. 0.1 11 table 6. dma crossbar channel peripheral assignments for sim3l1xx devices peripheral dma channel 0 dma channel 1 dma channel 2 dma channel 3 dma channel 4 dma channel 5 dma channel 6 dma channel 7 dma channel 8 dma channel 9 dtm0 a ? dtm0 b ? dtm0 c ? dtm0 d ? dtm1 a ? dtm1 b ? dtm1 c ? dtm1 d ? dtm2 a ? ? dtm2 b ? ? dtm2 c ? ? dtm2 d ? ? spi0 tx ? ? ? spi0 rx ? ? ? encdec0 tx ? ? encdec0 rx ? ? aes0 tx ? ? aes0 rx ? ? aes0 xor ? ? spi1 tx ? ? spi1rx ? ? usart0 tx ? ? ? ? usart0 rx ? ? ? ? i2c0 rx ? ?? ?? ?? i2c0 tx ? ? ? ? saradc0 ? ? ? ?
AN666 12 rev. 0.1 idac0 ? ? ? ? epca0 capture ?? ? ?? epca0 control ? ?? ? timer0l overflow ? ? ? ? ? timer0h overflow ? ? ? ? ? timer1l overflow ? ? ? ? ? timer1h overflow ? ? ? ? ? dmaxt0 ? ? ? ? ? dmaxt1 ? ? ? ? ? software trigger ?????????? table 6. dma crossbar channel peripheral assignments for sim3l1xx devices (continued) peripheral dma channel 0 dma channel 1 dma channel 2 dma channel 3 dma channel 4 dma channel 5 dma channel 6 dma channel 7 dma channel 8 dma channel 9
AN666 rev. 0.1 13 4.3. transfer types the dma channels support five transfer types: basic, auto-request, ping-pong, memory scatter-gather, and peripheral scatter-gather. table 7 shows the memory requirements for each transfer type. 4.3.1. basic transfers the basic transfer type uses only one descriptor (primary or alternate). in this mode, the channel will make ncount + 1 data moves in 2 rpower bursts. each data request moves one 2 rpower set of data. the number of requests required for a transfer is: equation 1. number of requests for basic transfers any data remaining can be transferred by firmware or use an extra dma data request. after the final data transfer: 1. the dma channel will write the pr imary descriptor tmd field with 0. 2. the primary descriptor ncount field will contain 0. 3. the controller automa tically disables the channel (the channel bit in chenset will read 0). figure 4 illustrates the dma memory descriptors for a basic transfer. this transfer type is recommended for peripher al-to-memory or memory-to-peripheral transfers. table 7. transfer memory requirements transfer type transfer descriptors required maximum memory (ram) required (bytes) address offsets (primary / alternate) primary alternate scatter- gather 10 channels implemented 16 channels implemented 10 or 16 channels implemented basic ? 160 256 0 / ? auto-request ? 160 256 0 / ? ping-pong ?? 320 512 0 / 256 memory scatter-gather ??? 320 + sg 512 + sg 0 / 256 + sg peripheral scatter-gather ??? 320 + sg 512 + sg 0 / 256 + sg number of requests ncount 1 + 2 rpower ------------------------------------ - =
AN666 14 rev. 0.1 figure 4. basic and auto-request transfer memory configuration 4.3.2. auto-request transfers auto-request transfers use only one descriptor (primary or alternate). this transfer type only requires one data request to transfer all of the data. the controller will arbitrate as normal (every 2 rpower transfers), and a channel interrupt will occur when th e transfer completes. this transfer type is reco mmended for memory-to-memory transfers. after the final data transfer: 1. the dma channel will write the pr imary descriptor tmd field with 0. 2. the primary descriptor ncount field will contain 0. 3. the controller automa tically disables the channel (the channel bit in chenset will read 0). the auto-request memory configuration is iden tical to the basic transfer shown in figure 4. abaseptr sim3xxxx address space (ram) srcend dstend config baseptr channel 0 primary structures
AN666 rev. 0.1 15 4.3.3. ping-pong transfers ping-pong transfers use both the primary and alternate channel descriptors. when the channel completes the transfer described by the first descriptor, it clears the tmd field in the original descriptor to 0 and toggles to point to the other descriptor. a channel interr upt will occur to allow firmware to upd ate the completed transfer?s descriptor, as the ping-pong operation will stop without intervention. as with basic transfers, each 2 rpower data moves require a new data request. the number of requests is given by equation 1. figure 5 shows an example where a channel?s primary descr iptor has an rpower of 1 with an ncount of 3 and the alternate descriptor has an rpower of 0 with an nc ount of 4. these descriptors are both configured to move words (dstsize and srcsize set to 2) in ping-pong mode (tmd = 3). figure 6 illustrates the ping- pong memory configuration. figure 5. ping-pong transfer example dma channel 0 primary structure (rpower = 1, ncount = 3) alternate structure (rpower = 0, ncount = 4) idle data request primary structure (rpower = 0, ncount = 3) firmware data request primary structure tmd set to 0, channel switches to alternate moves 2 words dma channel interrupt idle or performing other tasks loads primary structure loads alternate structure idle data request idle data request idle data request alternate structure tmd set to 0, channel switches to primary moves 1 word moves 1 word moves 2 words idle or performing other tasks loads primary structure dma channel interrupt idle or performing other tasks passes through isr, data moves are done moves 1 word data request moves 1 word dma channel interrupt idle moves 1 word primary structure tmd set to 0, all transfers stop until firmware configures a structure passes through isr, data moves are done data request
AN666 16 rev. 0.1 figure 6. ping-pong transfer memory configuration abaseptr sim3xxxx address space (ram) srcend dstend config baseptr channel 0 primary structures srcend dstend config channel 0 alternate structures
AN666 rev. 0.1 17 4.3.4. memory scatter-gather transfers the memory scatter-gather transfer uses primary, alte rnate, and scatter-gather desc riptors. this transfer type allows a dma channel to be set for multiple transfers at on ce without core intervention at the price of extra memory for the scatter-gather descriptors. the primary descriptor in this mode contains the numb er and location of the scatter-gather descriptors. the primary descriptor should be programmed as follows: 1. memory scatter-gather primary mode (tmd = 4). 2. rpower = 2. 3. ncount set to the va lue specified by equation 2. 4. srcend is set to the location of the la st word of all the scatter-gather descriptors. 5. dstend is set to the location of the la st word in the single alternate descriptor. equation 2. ncount value for scatter-gather transfers the scatter-gather descriptors must be stacked contiguous ly in memory. the channel will copy the scatter-gather descriptors into the alternate descriptor location and execute them one by one. the scatter-gather descriptors should be programmed to memory scatter-gather alternate mode (tmd = 5), except for the last descriptor, which should use the auto-request transfer type (tmd = 2). once started, the dma channel execution process is as follows: 1. copy scatter-gather 1 (s g1) to the alternate descriptor. 2. jump to the alternate descriptor and execute. 3. jump back to the primary descriptor. 4. copy scatter-gather 2 (s g2) to the alternate descriptor. 5. jump to the alternate descriptor and execute. 6. jump back to the primary descriptor. the channel will continue in this pattern until the channel encounters a scatter-g ather descriptor set to a basic or auto-request transfer. only one data request is required to execute all of the scattered transaction s. the channel interrupt will occur once the last scatter-gather descriptor (programmed to a basic transfer) executes, if enabled. arbitration occurs every 2 rpower of the scatter-gather descriptors. figure 7 shows the memory scatter-gather memory configuration. ncount number of sg structures 4 ? ?? 1 ? =
AN666 18 rev. 0.1 figure 7. memory and peripheral scatter-gather transfer memory configuration abaseptr sim3xxxx address space (ram) baseptr primary structures alternate structures srcend dstend config channel 0 sg 1 srcend dstend config channel 0 sg 2 (optional) scatter-gather structures srcend dstend config channel 0 srcend dstend config channel 0
AN666 rev. 0.1 19 4.3.5. peripheral scatter-gather transfers the peripheral scatter-gather transfer is very similar to the memory scatter-gather transfer and uses primary, alternate, and scatter-gather descriptors. this transfer type allows a dma chan nel to be set for mu ltiple transfers at once without core intervention at the price of extra memory for the scatter-gather descriptors. a data request is required for each 2 rpower data move of the scatter-gather descriptor tasks. the rpower value can be different for each scatter-gather task. equation 1 describes the total number of data requests required to complete a transfer. the primary descriptor in this mode contains the numb er and location of the scatter-gather descriptors. the primary descriptor should be programmed as follows: 1. peripheral scatter-gather primary mode (tmd = 6). 2. rpower = 2. 3. ncount set to the va lue specified by equation 2. 4. srcend is set to the location of the la st word of all the scatter-gather descriptors. 5. dstend is set to the location of the la st word in the single alternate descriptor. the scatter-gather descriptors must be stacked contiguous ly in memory. the channel will copy the scatter-gather descriptors into the alternate descriptor location and execute them one by one. the scatter-gather descriptors should be programmed to peripheral scatter-gather alternate mode (tmd = 7), except for the last descriptor, which should use the basic transfer type (tmd = 1). once started, the dma channel execution process is as follows: 1. copy scatter-gather 1 (s g1) to the alternate descriptor. 2. jump to the alternate descriptor and execute. 3. jump back to the primary descriptor. 4. copy scatter-gather 2 (s g2) to the alternate descriptor. 5. jump to the alternate descriptor and execute. 6. jump back to the primary descriptor. the channel will continue in this pattern until the channel encounters a scatter-g ather descriptor set to a basic or auto-request transfer. the channel interr upt will occur once the last scatt er-gather descriptor (programmed to a basi c transfer) executes, if enabled. figure 7 shows the peripheral scatter-gather memory configuration.
AN666 20 rev. 0.1 4.4. data requests each dma channel has two data requests: single and burst. peripherals can support single requests, burst requests, or both. if configured to use a dma channel, peripherals request data as needed using the appropriate request type. table 8 and table 9 lists the supported requests for the supported triggers and peripherals. the rpower field is only valid for peripherals that suppor t burst requests. for peripherals that only support single requests, the rpower field is ignored and re-arbitration occurs after every single data move. table 8. supported trigger or peripheral data requests for sim3u1xx/sim3c1xx devices peripheral module supported request types number of data transfers per data request rpower setting data size aesn burst only 4 2 word epcan burst only 1, 2, 4, or 8 0, 1, 2, or 3 word i2cn single only 1 unused word i2sn burst only 1 or 4 0 or 2 word idacn burst only 1 0 word saradcn burst only 4 2 word spin burst only 1, 2, 4, or 8 0, 1, 2, or 3 byte timern overflow burst only any any byte, half-word, or word usartn single only 1 unused byte, half-word, or word usbn both 1, 2, 4, or 8 0, 1, 2, or 3 word external trigger burst only a ny any byte, half-word, or word software trigger burst only any any byte, half-word, or word
AN666 rev. 0.1 21 in addition to peripheral-initia ted transfers, all of the su pported dma channels can sele ct the rising or falling edges of one of the dma external transfer start signals to init iate data transfers. when the selected edge occurs on the external signal, the dma channels with the dma0t0/1 signals selected in the dmaxbarx.channsel field will start the corresponding channel?s data transfer as defi ned by the dma channel data descriptor in memory. the dma module external trigger sources are routed to peripheral pins using the crossbar. 4.5. masking channels dma channels can be temporarily disabled by setting the channel bit in chreqmset. setting this bit to 1 causes the dma channel to no longer resp ond to data requests from peripherals. the chann el will always respond to software-initiated transfer requests, even if chreqmset is set for the channel. firmware can write a 1 to the chreqmclr register to clear the mask for a channel. it is recommended that firmware se t the channel request mask (chreqm set) for channels using software- initiated transfers to avoid any peripherals connected to the channel from requesting dma transfers. 4.6. errors the error bit in the berrclr register indicates when a dma bus error occu rs. if enabled, this bit will generate an interrupt. table 9. supported trigger or peripheral data requests for sim3l1xx devices peripheral module supported request types number of data transfers per data request rpower setting data size aesn burst only 4 2 word epcan burst only 1, 2, 4, or 8 0, 1, 2, or 3 word i2cn single only 1 unused word encdecn single only 1 unused byte, half-word, or word, depending on the mode dtmn burst only varies based on the peripheral varies based on the peripheral varies based on the peripheral idacn single only 1 unused word saradcn burst only 4 2 word spin burst only 1, 2, 4, or 8 0, 1, 2, or 3 byte timern overflow burst only any any byte, half-word, or word usartn single only 1 unused word external trigger burst only a ny any byte, half-word, or word software trigger burst only any any byte, half-word, or word
AN666 22 rev. 0.1 4.7. arbitration the dma controller is a master on the ahb bus. this a llows the module to control data transfers without any interaction with the core. the channels are in a fixed priority order. channel 0 has the highest priority, and the last implemented channel has the lowest priority. this fixed order can be superce ded by using the programmable high priority setting (chhpset). at each re-arbitrati on period, the controller give s control of the bu s to the highest pr iority channel with a pending data request. the rpower field in the channel transfer descriptors determines when the re-arbitration periods occur. the channel in control of the bus will make 2 rpower data moves before the controller re-arbitrates. if the channel still has the highest priority, it can transfer again until the next re-arbitration period. the rpower field is only valid for peripherals that support burst requests. for peripherals that on ly support single request s, re-arbitration will occur after each single data move. figure 8 shows an example controller arbitration with two channels active. channel 0 has an rpower of 1 (2 data moves), and channel 1 has an rpower of 0 (1 data move). both channels are set to move words (dstsize and srcsize set to 2). figure 8. dma arbitration example 4.8. fast mode the sconfig module contains a bit (fdmaen) that e nables faster dma transfer s when set to 1. it is recommended that all applications using the dma set this bit to 1. idle idle channel 0 (rpower = 1) idle idle data request data request channel 1 (rpower = 0) re-arbitration period channel 0 has a pending request and highest priority data request data request re-arbitration period channel 0 has a pending request and highest priority re-arbitration period no pending data requests idle moves 1 word moves 2 words moves 2 words data request idle moves 1 word moves 1 word re-arbitration period channel 1 has a pending request and highest priority
AN666 rev. 0.1 23 5. using the dma for a memory-to-memory transfer the memory-to-memory transfer is the most basic dma o peration since it doesn?t require the interaction with a peripheral. a memory-to-memory transfer can use the auto-request dma transfer type. figure 9. memory-to-memory dma transfer to configure a dma channel for a memory-to-memory data transfer: 1. enable the ahb and apb clocks to the dma controller. 2. enable the dma module (dmaen = 1). 3. set the addre ss location of the channel trans fer descriptors (baseptr) accord ing to the restrictions in section ?4.1. dma channe l transfer descriptors?. 4. use the chaltclr register to set the channel to use the primary descriptor. 5. create the primary descriptor in memory for the desired transfer: a. set the srcend field to the last address of the source data. b. set the dstend field to the last address of the destination memory. c. set the destination and source address incremen t modes (dstaimd and srcaimd). in most cases, these values should be the same. d. set the destination and source data size (dstsize and srcsize) to the same value. e. set the rpower to the desired number of data tran sfers between rearbitration. in most cases, this value can be 0. f. set the ncount field to the total number of transfers minus 1. g. set the transfer mode to the auto-request type (tmd = 2). 6. disable data requests for the channel using the chreqmset register. 7. set the dma to fast mode using th e fdmaen bit in the sconfig module. 8. enable the dma channel using the chenset register. 9. (optional) enable the dma channel interrupt. 10. submit a request to start the transfer. sim3xxxx address space (ram) dma channel 0
AN666 24 rev. 0.1 for memory-to-memory transfers that do not rely on a peri pheral, the easiest way to initiate these transfers is to use the software request in the chswrcn register. it is recommended that firmware set the channel request mask (chreqmset) for channels using software-initiated transfers to avoid any peripherals connected to the channel from requesting dma transfers. alternate start-of-transfer triggers could be the external triggers (dmaxt0 or dmaxt1) or a timer overflow trigger. the dma_memory_to_memory.c code example included in the software package demonstrates this type of dma transfer.
AN666 rev. 0.1 25 6. using the dma for a peripheral-t o-memory or memory-to-peripheral transfers a peripheral-to-memory or memory-to-peripheral transfer can use the basic dma transfer type. figure 10. peripheral-to-memory dma transfer figure 11. memory-to-peripheral dma transfer sim3xxxx address space (ram) dma channel 0 usart0 rx sim3xxxx address space (ram) dma channel 1 usart0 tx
AN666 26 rev. 0.1 to configure a dma channel for a peripheral-to-memory (recei ve) or memory-to-peripheral (transmit) data transfer: 1. enable the ahb and apb clocks to the dma controller. 2. enable the dma module (dmaen = 1). 3. set the addre ss location of the channel transfer descriptors (baseptr). 4. route the dma signals from the peripheral function to a dma channel. 5. use the chaltclr register to set the channel to use the primary descriptor. 6. create the primary descriptor in memory for the desired transfer: a. set the srcend field to the last address of the source data. b. set the dstend field to the peripheral fifo register. c. set the destination and source address increment modes (dstaimd and srcaimd). for peripheral- to-memory transfers, the source should be in non-incrementing mode. for peripheral-to-memory transfers, the destination should be in non-incrementing mode. d. set the destination and source data size (dstsize and srcsize) to the same value. e. set the rpower to the desired number of data transfers between rearbitration. see the appropriate rpower value for the peripheral (table 4, table 5, and table 6). f. set the ncount field to the to tal number of transfers minus 1. g. set the transfer mode to the basic type (tmd = 1). 7. enable data requests for the channel (chreqmclr). 8. set the dma to fast mode using th e fdmaen bit in the sconfig module. 9. enable the dma channel using the chenset register. 10. (optional) enable the dma channel interrupt. 11. enable the peripheral to start the transfer. the chaltset register can set a dma channel to use the alternate descriptor instead of the primary descriptor. firmware can use the chaltclr register to set the channel back to the primary descriptor. the controller automatically updates the chaltset fields to indicate wh ich descriptor is in use during transfers that use the alternate descriptor (ping-pong and scatter-gather). the dma_peripheral_to_memory.c code example included in the software package demonstrates a peripheral- to-memory dma transfer by using the usart0 peripheral (receive only) to receive ascii characters from the cp210x usb-to-uart bridge on the mcu card and store them in memory. the characters can be entered using a terminal program on the pc. the dma_memory_to_ peripheral.c code example included in the software package demonstrates a memory-to- peripheral dma transfer by using the usart0 peripheral (transmit only) to transmit an ascii table stored in memory to the cp210x usb-to-uart bridge on the mcu ca rd. the table is displayed in a terminal program on the pc.
AN666 rev. 0.1 27 7. using the dma for a delayed peripheral-to-memory-to-peripheral transfer the ping-pong data transfer allows a single dma channel to perform multiple actions. after the first transfer described by the primary descriptor comp letes, the dma channel will automatically transition to the transfer in the alternate descriptor. to stop the dma, load the last descr iptor with a basic transfer type (tmd = 1). the dma will interrupt after each ping-pong transfer completes. figure 12. peripheral-to-memory-to-peripheral dma transfer to configure a dma channel for ping-pong data transfer: 1. enable the ahb and apb clocks to the dma controller. 2. enable the dma module (dmaen = 1). 3. set the addre ss location of the channel transfer descriptors (baseptr). 4. route the dma signals from the peripheral function to a dma channel. 5. use the chaltclr register to set the channel to use the primary descriptor. 6. create the primary descriptor in memory for the desired transfer: a. set the srcend field to the last address of the source data. b. set the dstend field to the peripheral fifo register. c. set the destination and source address increment modes (dstaimd and srcaimd). for peripheral- to-memory transfers, the source should be in non-incrementing mode. for peripheral-to-memory transfers, the destination should be in non-incrementing mode. d. set the destination and source data size (dstsize and srcsize) to the same value. e. set the rpower to the desired number of data transfers between rearbitration. see the appropriate rpower value for the peripheral. f. set the ncount field to the to tal number of transfers minus 1. g. if this is the last action for the dma channel , set the transfer mode to the basic type (tmd = 1). otherwise, set the transfer mode to the ping-pong type (tmd = 3). sim3xxxx address space (ram) dma channel 1 dma channel 0 usart0 rx usart0 tx
AN666 28 rev. 0.1 7. create the alternate descriptor in memory for the desired transfer: a. set the srcend field to the last address of the source data. b. set the dstend field to the peripheral fifo register. c. set the destination and source address increment modes (dstaimd and srcaimd). for peripheral- to-memory transfers, the source should be in non-incrementing mode. for peripheral-to-memory transfers, the destination should be in non-incrementing mode. d. set the destination and source data size (dstsize and srcsize) to the same value. e. set the rpower to the desired number of data transfers between rearbitration. see the appropriate rpower value for the peripheral. f. set the ncount field to the to tal number of transfers minus 1. g. if this is the last action for the dma channel , set the transfer mode to the basic type (tmd = 1). otherwise, set the transfer mode to the ping-pong type (tmd = 3). 8. enable data requests for the channel. 9. set the dma to fast mode using th e fdmaen bit in the sconfig module. 10. enable the dma channel using the chenset register. 11. (optional) enable the dma channel interrupt. 12. submit a request to start the transfer. the dma_peri_to_mem_to_peri.c code example included in the software package demonstrates a ping-pong dma transfer by using the usart0 peripheral (transmit and receive) to receive 2 10-byte character sets from a terminal program on the pc using the cp210x usb-to -uart bridge on the mcu card. when the second set is received, a second dma channel displays the received ch aracters in the terminal program on the pc. this code example uses two different dma channels due to the dma peripheral crossbar mapping and since both the usart0 receive and usart0 transmit features are used. 8. using the dma for a simultaneous peripheral-to-memory-to-peripheral transfer a single dma channel is unable to service more than one peripheral simultaneously. in addition, dma channels cannot automatically start or pause a transfer in another channel without core intervention. the easiest way to perform a peripheral-to-memory-to-perip heral transfer (i.e., i2c-to-m emory-to-uart) is to set up several buffers in memory. once the first peripheral transfers data to the first buffer, the dma channel done interrupt will occur, if enable d. inside this interr upt service routine, firmware ca n start the first dma channel to transfer data from the source peripheral to a second buffer and set up a second dma channel to transfer data from the first buffer to the end peripheral. the dtm module on sim3l1xx devices allows these types of transfer to occur without core intervention.
AN666 rev. 0.1 29 9. dtm overview (sim3l1xx devices only) the dtm module collects dma request signals from various peripherals and generates a series of master dma requests based on a state-driven configuration. this master request drives a set of dma channels to perform functions such as asse mbling and transferring communication packets to external radio periphe rals. this capability saves power by allowing the mcu to remain in low power modes such as pm2 during complex transfer operations. a combination of simple and peripheral-scatter-gather dma configurations can be used to perform complex operations while limiting the memory requirements (for ex ample, by implementing direct peripherals-to-peripheral transfers). each dtm block supports up to 15 user-configurable states. each state can be set up to run a certain number of dma operations from one peripheral (the source) to an other (the destination), including memory areas such as flash and ram. each state also has the ability to define two options for what the ne xt state in the sequence will be, dependent on the condition of the counters and other parameters in the dtm block. each dtm block is capable of driving up to four dma channels (a, b, c and d), and each dtm state can be configured to drive a particular request line to the dma. this allows basic dma operations to replace a long sequence of peripheral-scatter-gather tas ks in most applications, saving memory. 9.1. counters the dtm modules contain three different counters: a master counter, a state counter, and a timeout counter. the 16-bit master counter, represented in the mstcount register, can be initia lized by firmware to track the number of dma requests that have occurred. mstcount is dec remented on each dma operation unless the active state configuration spec ifies otherwise. the 8-bit state counter, represented by the stcount field in the control register, also decrements each time a dma request is generated. this is used to track the nu mber of requests since the active state was last entered (from 1 to 256). the stcount field is automatically loaded with the value of streload in the state description when a state is entered. a 16-bit timeout counter is represented by the tocount fi eld in the timeout register. an internal 8-bit prescaler divides the apb clock frequency and tocount is dec remented every 256 apb cloc k cycles. each state can selectively reload tocount and enable or disable the timeout counter while the state is active. if a tocount reload is requested, t he timeout counter will be reloa ded from the torelo ad field in the ti meout register, and the internal prescaler will reset. if tocount reaches 0 and the internal pr escaler overflows, a timeout error is declared and the dtm transitions to its done state. the toerri fl ag in the control register will be set and an interrupt will be gen erated if enabled. when it is used, the length of the timeout is equal to 256 x (treload + 1) apb clock cycles.
AN666 30 rev. 0.1 9.1.1. state machine control each of the 15 available states in a dtm block has co nfiguration information which defines the state operation when it is active. states are set up by firmware in the ram or flash region of the dev ice, and when a state becomes active, its information is read into the dtm block?s state register. 9.1.2. source, destination, and dtm channel the srcmod and dstmod fields define the source trigger and the destination trigger for the transfers that will occur in the active state. the available sources and de stinations are detailed in table 10 and table 11. if the required dma transfer is going to or from a memory location, the value 1111b (0xf) should be used in the corresponding field. table 10. dtm source module options srcmod source srcmod source 0000 spi0 receive 1000 epca0 capture 0001 spi1 receive 1001 encdec0 output 0010 aes0 output 1010 reserved 0011 reserved 1011 reserved 0100 usart0 receive 1100 reserved 0101 reserved 1101 dma0t0 0110 i2c0 receive 1110 dma0t1 0111 saradc0 output 1111 memory transfer (no source) table 11. dtm destination module options dstmod destination dstmod destination 0000 spi0 transmit 1000 epca0 capture 0001 spi1 transmit 1001 encdec0 input 0010 aes0 data in 1010 reserved 0011 aes0 xor in 1011 reserved 0100 usart0 transmit 1100 reserved 0101 reserved 1101 dma0t0 0110 i2c0 transmit 1110 dma0t1 0111 idac0 input 1111 memory transfer (no destination)
AN666 rev. 0.1 31 when a given state is active, the dtm waits until both its source and destination peripherals have asserted their dma request signals, indicating that both are ready to tran smit/receive dma traffic. at this time, the dtm asserts its master dma request signal for the channel specified in the state?s dtmchsel field, causing the dma engine to perform the next task in that channel?s sequence of operat ion. this dma task satisfies the source and destination peripheral requests by moving data from the source to the destination. in general, the source and destination peripherals will not be assigned to a dma channel in the dma crossbar , and all related dma traffic will be requested by the dtm. 9.1.3. state transitions each state is associated with a number, 0 through 14. the number 15 is reserved for a done state, which terminates dtm operations. the states define two possible paths for the next state, defined in the prist (primary state) and secst (secondary state) fields of the state st ructure. these two fields may be loaded with any valid state value, including 15 (the done state). a simple representation of the dtm state transitions is shown in figure 13. figure 13. state transition diagram when a state is entered, it becomes the active state. its information is loaded from memory into the state register, and its state number will be reported in the st field of the control register . at the same time, the state counter (stcount) will be loaded with the value in the state?s streload field. while a state is active, the dtm will manage the data transfer between the selected source and destination peripherals, using the selected dtm channel to request dma operation s. the operation will last as long as the dma is still ac tively transferring the data. after the transfer is complete, the state counter is decremen ted. if the mstdecen bit in the state structure is set to 1, the master counter will also be decremented. if the master counter is non-zero and the state counter is equal to zero, the state ma chine will transition to the primary state defined by prist. if the master counter reaches zero and either the state counter is zero or mstdecen = 1, the state machine will transition to the secondary state def ined by secst. finally, if a timeout error occurs (tocount reaches zero) when timeouts are enabled, or if a dma error occurs for the selected channel, the state machine will transition to the done stat e and generate the appropriat e flags. upon exit from a state, the value of that state is loaded into the lastst field in the control register. in some scenarios, a state will need to remain active until mstcount reac hes zero, even if there are more than 256 requests generated. in such cases, this is accomp lished by setting the value of prist to the active state number. active state done primary state (prist) secondary state (secst) state counter = 0 and master counter > 0 (state counter = 0 or mstdecen = 1) and master counter = 0 dma error or timeout event
AN666 32 rev. 0.1 it is also possible to instruct a state to hold off any further transfer requests until an external pin input (specified by the inhsel field in the control register) is asserted . the dtminh and inhspol fields in the state structure configure this capability fo r the selected inhibit pin. 9.1.4. interrupts within a state structure, the user can selectively enable timeout interrupts and state transition interrupts. the timeout counter and its associated interrupt are e nabled using the toerrien flag. if tioerrien is set, tocount is loaded with the value of toreload on entry into the state. if the toco unt field reaches zero, the tioerri interrupt flag will be set, and the state mach ine transitions to done. the pristien and secstien flags enab le interrupts upon transition to the primary and secondary states, respectively. when either of these interrupts occurs, the dt mi interrupt fl ag will be set by hardware. 10. using the dtm module on sim3 l1xx devices for peripheral-to-memory- to-peripheral transfers the dtm allows dma channels to automatically chain without core intervention. when creating dtm code, it is recommended to first start with the basic peripheral config uration and verify the peripheral is configured correctly before adding dma support. once the dma operation is veri fied, add the final dtm piece to create the full system. to set up a dtm system: 1. enable ahb and apb clocks to the dtm module. 2. start with dtm/dma channels disabled. 3. configure the dma channel or channels. ensure the dma crossbar maps the dma channels to dtm channels. wait to enable the channels until after the dtm mo dule is completely initialized. 4. initialize the state fields fo r the dtm operation. for each state: a. set the dtm channel for the state (a, b, c, or d). b. set the source field (srcmod). c. set the destination field (dstmod). d. select the next state for the primary state transition (prist). e. select the next state for the secondary state transition (secst). f. set the number of dma transfers for the state using the streload field. g. set any active interrupts or other options for the state. 5. initialize the dtm module. 6. clear all interrupts in the dtm module. 7. (optional) enable dtm module interrupts. 8. enable the dtm module and dma channels. the dtm_peri_to_mem_to_peri.c code example included in the software package demonstrates two basic dma transfers using the usart0 peripheral (transmit and rece ive) to receive and transmit a 20-byte character set from and to a terminal program on the pc using the cp210x usb-to-uart bridge on the mcu card. the dtm automatically starts the transmit dma transfer after the receive dma transfer, displaying the characters in the terminal program on the pc. this code example uses two different dma and dtm0 channels for the two states s0 (receive) and s1 (transmit).
AN666 rev. 0.1 33 figure 14. dtm peripheral-to-memory-to-peripheral example sim3xxxx address space (ram) dma channel 1 dma channel 0 usart0 rx usart0 tx dtm module channel a channel b s0 (a) done s1 (b)
AN666 34 rev. 0.1 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. patent notice silicon labs invests in research and development to help our cust omers differentiate in the market with innovative low-power, s mall size, analog- intensive mixed-signal soluti ons. silicon labs' extensive pat ent portfolio is a testament to our unique approach and world-clas s engineering team. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

▲Up To Search▲

Price & Availability of AN666

	To Download AN666 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .